1. Field of the Invention
The present invention relates generally to a method for providing dielectric insulation regions for electrical isolation between transistors of an integrated circuit or circuits on the same semiconductive substrate. More particularly the present invention relates to a method for providing, between n-channel field effect transistors (FETs) located on the same semiconductive substrate, dielectric isolation regions with an extra p-type parasitic channel stopper doping self-aligned with respect to the dielectric isolation. Furthermore, the present invention provides enhancement-mode (i.e., normally-off) FETs having a gate threshold voltage which is advantageously increased to a more positive value by the addition of a p-type dopant in the channel region of the substrate.
2. Description of the Prior Art
It is known in the prior art that integrated circuits containing many thousands of transistors on a single semiconductive substrate or chip may be fabricated. Such a semiconductor chip typically measures one quarter of one inch on a side, or less. A major concern in the fabrication of integrated circuits is the means by which the transistors on the substrate may be electrically isolated one from another wherever desired. More particularly, the doped source and/or drain regions of one FET must be prevented from electrically shorting to the source and/or drain regions of an adjacent FET.
Methods for electrically isolating adjacent FETs on the same substrate are known in the art. FETs may be formed by using the p-channel (PMOS) technology (i.e., n-type doped substrate), or by using the n-channel (NMOS) technology (i.e., p-type doped substrate). Of these, the p-channel technology is simpler to fabricate in part because the n-type dopant in the substrate tends to accumulate at the substrate surface near the interface with a thick, thermally-grown, field-isolation oxide, thereby naturally providing additional protection against parasitic conductive channels that might otherwise form beneath the field oxide. The n-channel technology, however, is preferred because of the inherently higher surface mobility which gives a shorter device switching time. Unfortunately, when an oxide layer is grown on a p-type substrate, the p-type dopant such as boron is disadvantageously depleted from the semiconductor surface by the growing oxide. The boron remains inert in the oxide. This well known boron depletion effect is described for example by Grove, Leistiko, and Sah in "Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon", Journal of Applied Physics, vol. 35, number 4, pp. 2695-2701, Sept. 1964.
When boron depletion occurs, parasitic conductive channels may form beneath the thick field oxide due to the presence of an electric field caused by oxide charges or by interconnection lines with a positive potential. Thus, in order to stop parasitic channels from forming the p-type dopant lost from the semiconductive surface must be replenished from deeper in the substrate, or augmented by an additional doping step. In the former case the semiconductive substrate is relatively heavily doped p-type to begin with, typically 2 ohm-cm (i.e. 7.5.times.10.sup.15 dopant atoms per cm.sup.3). The field oxide is provided by thermally growing a thick silicon dioxide layer over the entire surface of the silicon substrate in the presence of steam at a relatively high processing temperature of about 1000.degree. C. This causes considerable boron depletion in the silicon substrate near the silicon-silicon dioxide interface. Later in the fabrication process, device regions are opened in the thick oxide by lithographic delineation and by etching, the FET gate insulator is formed, the gate regions are defined, and the n-type source and drain regions are formed. Formation of the gate insulator and the source/drain regions involves high processing temperatures during which p-type doping impurities diffuse to the silicon surface from the relatively heavily doped silicon bulk. Thus the use of a relatively heavily doped p-type silicon substrate allows the depleted surface doping to be returned near enough to its original value that surface inversion can be prevented.
The use of a relatively highly doped substrate, however, offers several problems. One is that the depletion layer capacitance of n-type source and drain regions is relatively larger, being proportional to the square root of the substrate doping concentration. Another problem is that the highly doped substrate is somewhat incompatible with channel implantation and hence threshold adjustment of the enhancement-mode device is usually accomplished with substrate bias. Yet another problem is that the gate threshold voltage sensitivity to changes in the source-to-substrate bias (i.e., the FET substrate sensitivity) is detrimentally enhanced by the higher substrate doping.
In fabricating FET integrated circuits it is generally preferable to use a relatively lightly doped substrate of the order of 5 to 15 ohm-cm (i.e., 2.5 to 1.0.times.10.sup.15 cm.sup.-3). This requires that additional p-type doping be provided to replace boron atoms depleted by a thermally grown field oxide, to augment the substrate doping in the field regions, and to prevent parasitic inversion layers from forming under the field oxide. An additional field doping is often referred to as a parasitic "channel stopper" region and may be formed by several known methods. One such approach has been described by R. J. Whittier in "Semiconductor Memories:, The Impact and Momentum of Current Technology", IEEE Electro 76 Meeting Tech. Digest, Session 33, FIG. 3B, p. 2, Boston, May 11, 1976. In this method an extra lithographic masking step is used to provide a p-type doped region that is not precisely registered with respect to the field oxide region. This technique requires a larger field oxide region due to the nonregistered nature of the channel stopper region, and an additional masking step which complicates the process.
A more recently developed isolation procedure, selective oxidation isolation, is shown in FIG. 3C of the abovementioned article by Whittier. In the selective oxidation technique, the masked regions used to selectively define the oxide isolation regions also are used to selectively block the p-type field doping from entering the device regions. Thus the field doping is self-aligned with respect to the field isolation regions and an extra lithographic masking step is not required. In addition, the self-alignment feature leads to smaller isolation regions. When the silicon surface is not etched prior to thermally growing the selective oxide, the oxide is partially recessed into the semiconductor surface. A processing sequence for the partially recessed oxide technique is described by Richman in "MOS Field-Effect Transistors and Integrated Circuits", Wiley-Interscience Pub., New York 1973, pp. 207-212. With silicon etching, the oxide may be grown fully recessed with respect to the silicon surface as described by Dennard, Rideout and Walker, "Method and Device for Reducing Sidewall Conduction in Recessed Oxide FET Arrays", U.S. Pat. No. 3,899,363, Aug. 12, 1975.
A difficulty with selective oxidation is that an oxidation barrier layer must be used to prevent oxidation in the device regions. Typically this oxidation barrier layer is of silicon nitride which is stable, inert, and simple to deposit. The mechanical properties of a silicon nitride layer are such, however that the underlying silicon surface tends to be strained and damaged. As a consequence, a padding layer of silicon dioxide is typically used under the silicon nitride oxidation barrier layer to reduce the strain. When the selective oxidation is performed, this oxide layer acts as a diffusion path for oxygen and detrimentally enhances the lateral oxidation thereby enlarging the selective isolation region as described by Bassous, Yu and Maniscalco, "The Formation of Bird's Beak in Silicon Structures with Recessed SiO.sub.2 ", ECS Fall Meeting Digest of Extended Abstracts, Dallas, Oct. 5-10, 1975, pp. 457-458. A further problem is that the chemical etchants for silicon nitride such as phosphoric acid (H.sub.3 PO.sub.4) can contaminate the silicon surface. Finally, a reaction with the nitride layer during thermal oxidation can lead to an unwanted nitride region being formed on the silicon surface near the growing oxide as described by Kooi, Van Lierop and Appels, "Formation of Silicon Nitride at an Si-SiO Interface During Local Oxidation of Silicon and During Heat Treatment of Oxidized Silicon in NH Gas", Paper 275 RNP, ECS Fall Meeting, Dallas, Oct. 9, 1975.